1. Field of the Invention
The present invention relates to a phase selector, and more particularly, to a phase selector with the functionality of deciding a phase of an output clock to trigger a flip-flop by comparing phases of an input data signal and an input clock.
2. Description of the Prior Art
In digital circuits, clock signals are essential reference signals for accessing digital data. Typically, latch time for accessing digital data in digital circuits is determined using either rising edge or falling edge triggers. In some cases, even though two different sub-circuits in a circuit system utilize exactly the same clock source, clocks and digital data transmitted to the sub-circuits may be asynchronous due to transmission delay or noise interference.
Take a transmitting device comprising two flip-flops as an example herein. Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic diagram illustrating digital data transmitted between two flip-flops 110 and 120. FIG. 2 is a timing diagram illustrating clocks and digital data in FIG. 1. An input data signal D1 and a clock C1 are used herein as inputs to the flip-flop 110, having waveforms and timing relation shown in FIG. 2. Assume that both flip-flops 110 and 120 are rising edge triggered, thus the input data signal D1 will be latched at t1, the flip-flop 110 will output latch data DL to the flip-flop 120, and the latch data DL will have a transition from “0” to “1” from t1, as shown in FIG. 2. Clocks C1 and C2 respectively for the two flip-flops 110 and 120 are asynchronous. Therefore, if a rising edge trigger of the clock C2 happens at t2 during the period when the latch data DL is changing from “0” to “1” as shown in FIG. 2, latch errors will be induced in the flip-flop 120, resulting in errors in digital data transmission.